1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to an advanced Faraday shield for a semiconductor device, such as an LDMOS device, and methods of making such a device.
2. Description of the Related Art
RF power amplifiers are key components in base stations, broadcast transmitters and microwave applications. Such power amplifiers can typically handle a wide range of signal types, such as GSM, EDGE, W-CDMA, WiMAX and DVD-T. LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices have been the technology of choice for RF power amplifiers for over a decade because of their excellent power capabilities, gain, efficiency and reliability. In an RF LDMOS device, a Faraday shield is usually employed for two purposes: (1) to screen the gate for drain potential and to move the high electric field away from the gate edge in an attempt to mitigate hot carrier injection at the drain edge under the gate; and (2) to reduce the reverse transfer capacitance (Cgd—gate to drain capacitance), thereby improving RF performance. As device dimensions continue to shrink, it becomes very important to develop devices with better shielding characteristics that can be manufactured in a cost-efficient and timely manner.
FIG. 1 is a simplified cross-sectional view of an illustrative prior art LDMOS semiconductor device 10 at an early stage of manufacturing. The LDMOS device 10 may be either an N-type LDMOS device or a P-type LDMOS device. The LDMOS device 10 is formed above an illustrative bulk semiconducting substrate 12 that may be comprised of silicon or other semiconducting materials. The substrate 12 may also have a silicon-on-insulator (SOI) configuration that includes a bulk silicon layer, a buried insulation layer and an active layer, wherein semiconductor devices are formed in and above the active layer.
As shown in FIG. 1, the LDMOS device 10 has an illustrative gate structure 14 formed above the substrate 12. The gate structure 14 is generally comprised of a gate insulation layer 14A and a gate electrode 14B, both of which may be comprised of a variety of materials and manufactured using a variety of known techniques. For example, the gate insulation layer 14A may be comprised of a variety of different materials, such as, for example, silicon dioxide, a so-called high-k (k greater than 10) insulation material, etc. Similarly, the gate electrode 14B may also be of a material such as polysilicon or amorphous silicon, or it may be comprised of one or more metal layers that act as the gate electrode 14B. Illustrative sidewall spacers 15 comprised of, for example, silicon nitride are typically formed adjacent the gate electrode structure 14 to protect and electrically isolate the gate electrode structure. The gate electrode 14B of the gate structure 14 has a source-side edge 14SE and a drain-side edge 14DE. A plurality of doped regions are formed in the substrate 12 as is customary for LDMOS devices, e.g., a source region 17, a drain region 19 and well contact regions 21. The device 10 also includes a plurality of isolation structures, e.g., trench isolation structures, formed in the substrate 10. More specifically, drain isolation region 16A separates the gate and the drain region 19, while the isolation regions 16B are positioned between the doped source/drain regions 17, 19 and the well contact regions 21.
Various conductive structures are formed in multiple layers of insulating material to provide electrical connection to various doped regions and structures of the LDMOS device 10. In the depicted example, the device 10 includes a plurality of conductive structures that are conductively coupled to the source/drain regions 17, 19 and the well contact regions 21 of the LDMOS device 10, namely source/drain region conductors (“SDC”) 20, source/drain contacts 22 (“CA”), so-called via zero (“V0”) 24 and metal-1 (“M1”) 26 conductive structures. Within the industry, the first general wiring layer for the integrated circuit product is typically designated “M1” and the source/drain region conductors 20 may sometimes be referred to as “trench silicide” regions. In the depicted example, the conductive structures are positioned in illustrative first, second and third layers of insulating material 30, 32, 34, respectively.
Also depicted in FIG. 1 is an “M-1” type Faraday shield 40 that extends laterally beyond the drain side edge 14DE of the gate electrode toward the drain region 19. Also schematically depicted in FIG. 1 is a so-called “WSi” type of shield 42 for the LDMOS device 10. In some cases, prior art LDMOS devices did not employ both types of shields. One purpose of the shields 40, 42 is to reduce the gate-to-drain (“Cgd”) capacitance so as to increase the RF performance and the switching speed of the LDMOS device. Additionally, the shields 40, 42 screen the gate from the potential applied to the drain 19 and effectively move the high electric field produced by the drain potential laterally away from the gate toward the drain region 19, which tends to reduce adverse hot carrier injection at the drain side edge 14DE of the gate electrode 14.
The present disclosure is directed to an advanced Faraday shield for a semiconductor device and methods of making such a device.